82845MP Datasheet, PDF (91/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.7.
BCC1 – Base Class Code Register – Device #1
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class Code of the MCH-M device #1. This code is 06h indicating a
Bridge device. This register is read only.
3.8.8.
Bit
Description
7:0
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the MCH-M
device #1. This code has the value 06h, indicating a Bridge device.
MLT1 – Master Latency Timer Register – Device #1
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read/Write
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-PCI bridge configuration software from getting “confused.”
3.8.9.
Bit
Description
7:3
Not applicable but supports read/write operations. (Reads return previously written data.)
2:0
Reserved
HDR1 – Header Type Register – Device #1
Offset:
Default:
Access:
Size:
0Eh
01h
Read Only
8 bits
This register identifies the header layout of the configuration space.
Bit
Descriptions
7:0
This read only field always returns 01h when read. Writes have no effect.
250687-002
Datasheet
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