82845MP Datasheet, PDF (16/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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1.2.1.
addresses lie within the AGP aperture are translated using the AGP address translation table, regardless
of the originating interface.
System Bus Error Checking
The Intel 845MP/845MZ Chipset MCH-M does not generate nor check parity for Data, Address/Request,
and Response signals on the processor bus.
1.3. System Memory Interface
The Intel 845MP/845MZ Chipset memory controller directly supports one channel of PC1600 or
PC2100 (845MZ PC1600 only) SO-DIMM DDR memory. The Intel 845MP/845MZ Chipset memory
interface supports DDR devices with densities of 64-Mb, 128-Mb, 256-Mb, and 512-Mb technology.
The maximum memory support is two, double-sided SO-DIMMs (four rows populated). The Intel
845MP/845MZ Chipset memory interface also supports variable page sizes of 2 KB, 4 KB, 8 KB, and 16
KB. Page size is individually selected for every row and a maximum of 16 pages may be opened
simultaneously.
Table 1. DDR Memory Capacity
Technology
845MP/845MZ Maximum
64 Mb
128 Mb
256 Mb
512 Mb
128 MB/128 MB
256 MB/256 MB
512 MB/512 MB
1 GB/ 512 MB
The memory interface provides optional ECC error checking for DRAM data integrity. During DRAM
writes, ECC is generated on a QWORD (64 bit) basis. Because the Intel 845MP/845MZ Chipset MCH-
M stores only entire cache lines in its internal buffers, partial QWORD writes initially cause a read of the
underlying data, and their write-back into memory is no different from that of a complete cache line.
During DRAM reads and the read of the data that underlies partial writes, the MCH-M supports
detection of single-bit and multiple-bit errors, and will correct single bit errors when correction is
enabled.
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Datasheet
250687-002