82845MP Datasheet, PDF (60/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.7.17.
DRT – DRAM Timing Register – Device #0
Offset:
Default:
Access:
Size:
78-7Bh
00000010h
Read/Write
32 bits
Bit
31:19
18:16
15:11
10:9
8:6
5:4
3
2
1
0
Description
Reserved
DRAM Idle Timer: This field determines the number of clocks the DRAM controller will remain in the
idle state before it begins precharging all pages.
000 Infinite
001 0
010 8 DRAM clocks
011 16 DRAM clocks
100 64 DRAM clocks
Others: reserved
Reserved
Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks for tRAS.
00 7 Clocks
01 6 Clocks
10 5 Clocks
11 Reserved
Reserved
CAS# Latency (tCL). This bit controls the number of DRAM Clocks between when a read command
is sampled by the SDRAMs and when the MCH-M samples read data from the SDRAMs.
00:
2.5
01:
2 Clocks
10:
Reserved
11:
Reserved
Reserved
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
Encoding tRCD
0:
3 DRAM Clocks (Default)
1:
2 DRAM Clocks
Reserved
DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
Encoding tRP
0:
3 DRAM Clocks(Default)
1:
2 DRAM Clocks
60
Datasheet
250687-002