82845MP Datasheet, PDF (93/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.8.13.
SMLT1 – Secondary Master Latency Timer Register – Device
#1
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
Read/Write, Read Only
8 bits
This register controls the bus tenure of the MCH-M on AGP. SMLT1 is an 8-bit register that controls the
amount of time the MCH-M as an AGP/PCI bus master, can burst data on the AGP Bus. The Count
Value is an 8-bit quantity, however SMLT1[2:0] are reserved and assumed to be 0 when determining the
Count Value. The MCH-M’s SMLT1 is used to guarantee the AGP master a minimum amount of system
resources. When the MCH-M begins the first AGP FRAME# cycle after being granted the bus, the
counter is loaded and enabled to count from the assertion of FRAME#. If the count expires while the
MCH-M’s grant is removed (due to an AGP master request), then the MCH-M will lose the use of the
bus, and the AGP master may be granted the bus. If MCH-M’s bus grant is not removed, the MCH-M
will continue to own the AGP bus regardless of the SMLT1 expiration or idle condition.
The number of clocks programmed in the SMLT1 represents the guaranteed time slice (measured in 66-
MHz AGP clocks) allotted to the MCH-M, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT1 is
programmed to 18h, then the value is 24 AGP clocks. The default value of SMLT1 is 00h and disables
this function. When the SMLT1 is disabled, the burst time for the MCH-M is unlimited (i.e. the MCH-M
can burst forever).
Bit
Description
7:3
Secondary MLT counter value. Default=0, i.e. SMLT1 disabled
2:0
Reserved
250687-002
Datasheet
93