82845MP Datasheet, PDF (69/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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Intel^® 82845MP/82845MZ Chipset-Mobile (MCH-M)
3.7.23.
SMRAM – System Management RAM Control Register – Device
#0
Address Offset:
Default Value:
Access:
Size:
9Dh
02h
Read/Write, Read Only, Lock
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated.
The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit
must be reset before the LOCK bit is set.
Bit
Description
7
Reserved
6
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made
visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK
is set to a 1, D_OPEN is reset to 0 and becomes read only.
5
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space DRAM. This
will allow SMM software to reference “through” SMM space to update the display even when SMM is
mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at
the same time.
Note that the D_CLS bit only applies to Compatible SMM space.
4
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,
D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become “Read Only”. D_LCK
can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The
combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to “lock down” SMM space in the
future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if
the program has knowledge of the D_OPEN function.
3
Global SMRAM Enable (G_SMRAME). If set to a 1, then Compatible SMRAM functions is enabled,
providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit has to be set to 1.
Once D_LCK is set, this bit becomes read only.
2:0
Compatible SMM Space Base Segment (C_BASE_SEG) (RO). This field indicates the location of
SMM space. “SMM DRAM” is not remapped. It is simply “made visible” if the conditions are right to
access SMM space, otherwise the access is forwarded to the hub interface. C_BASE_SEG is
hardwired to 010 to indicate that the MCH-M supports the SMM space at A0000h-BFFFFh.
250687-002
Datasheet
69