82845MP Datasheet, PDF (40/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
Bit
31
30:24
23:16
15:11
10:8
7:2
1:0
Descriptions
Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI configuration space are
enabled. If this bit is reset to 0, accesses to PCI configuration space are disabled.
Reserved (These bits are read only and have a value of 0).
Bus Number: When the Bus Number is programmed to 00h the target of the Configuration Cycle is a
hub interface agent (MCH-M, ICH3-M, etc.).
The Configuration Cycle is forwarded to hub interface if the Bus Number is programmed to 00h and the
MCH-M is not the target (the device number is >= 2).
If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS
NUMBER Register of device #1, a Type 0 PCI configuration cycle will be generated on AGP.
If the Bus Number is non-zero, greater than the value in the SECONDARY BUS NUMBER register of
device #1 and less than or equal to the value programmed into the SUBORDINATE BUS NUMBER
Register of device #1 a Type 1 PCI configuration cycle will be generated on AGP.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by device #1’s
SECONDARY BUS NUMBER or SUBORDINATE BUS NUMBER Register, then a hub interface Type 1
Configuration Cycle is generated.
Device Number: This field selects one agent on the PCI bus selected by the Bus Number. When the
Bus Number field is “00” the MCH-M decodes the Device Number field. The MCH-M is always Device
Number 0 for the Host-hub interface bridge entity and Device Number 1 for the Host-AGP entity.
Therefore, when the Bus Number =0 and the Device Number=0-1 the internal MCH-M devices are
selected.
If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS
NUMBER Register, a Type 0 PCI configuration cycle will be generated on AGP. The MCH-M will decode
the Device Number field[15:11] and assert the appropriate GAD signal as an IDSEL. For PCI-to-PCI
Bridge translation, one of the 16 IDSELs is generated. When bit [15] = 0 bits [14:11] are decoded to
assert a signal AD[31:16] IDSEL. GAD16 is asserted to access Device #0, GAD17 for Device #1 and so
forth up to Device #15 for which will assert AD31. All device numbers higher than 15 cause a type 0
configuration access with no IDSEL asserted, which will result in a Master Abort reported in the MCH-M’s
“virtual” PCI-PCI bridge registers.
For Bus Numbers resulting in hub interface configuration cycles, the MCH-M propagates the device
number field as A[15:11]. For bus numbers resulting in AGP type 1 configuration cycles, the device
number is propagated as GAD[15:11].
Function Number: This field is mapped to GAD[10:8] during AGP Configuration cycles and A[10:8]
during hub interface configuration cycles. This allows the configuration registers of a particular function in
a multi-function device to be accessed. The MCH-M ignores configuration cycles to its internal Devices if
the function number is not equal to 0.
Register Number: This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to GAD[7:2]
during AGP Configuration cycles and A[7:2] during hub interface Configuration cycles.
Reserved
40
Datasheet
250687-002