82845MP Datasheet, PDF(13/157 Page) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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82845MP Datasheet, PDF (13/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

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IntelÂ® 82845MP/82845MZ Chipset-Mobile (MCH-M)

IntelÂ® 845 Chipset MCH-M Features

Processor/Host Bus Support

ï£§ Supports the Mobile Intel Pentium 4 Processor-M

CPU

ï£§ Supports the Intel Pentiumï£¨ 4 processor subset of

the Enhanced Mode Scaleable Bus Protocol

ï£§ 2x Address, 4x Data

ï£§ Mobile Intel Pentium 4 Processor-M System Bus

interrupt delivery

ï£§ Supports system bus at 400 MT/s (100 MHz)

ï£§ Supports host bus Dynamic Bus Inversion (DBI)

ï£§ Supports 32-bit host bus addressing

ï£§ 12 deep In-Order Queue

ï£§ AGTL+ bus driver technology with integrated

AGTL termination resistors

Memory System

ï£§ Directly supports one DDR channel, 64b wide (72b

with ECC).

ï£§ Supports 200 and 266-MHz DDR compliant

devices (845MZ supports 200 MHz DDR only)

ï£§ Supports 64-Mb, 128-Mb, 256-Mb and 512-Mb

technologies for x16 devices and x8 devices.

ï£§ All supported devices have 4 banks

ï£§ Configurable optional ECC operation (single bit

Error Correction and multiple bit Error Detection)

ï£§ Supports up to 16 simultaneous open pages

ï£§ Supports page sizes of 2 KB, 4 KB, 8 KB, and 16

KB. Page size is individually selected for every

row.

ï£§ Thermal throttling scheme to selectively throttle

reads and/or writes. Throttling can be triggered by

preset read/write bandwidth limits.

ï£§ Max of 2 double-sided (4 rows populated) with

unbuffered PC2100 DDR (with or without ECC)

SO-DIMMs (845MZ supports only 200-MHz

DDR).

ï£§ Largest memory supported is 1 GB (845MZ

supports only up to 512 MB).

System Interrupts

ï£§ Supports only System Bus interrupt delivery

mechanism

ï£§ Supports interrupts signaled as upstream Memory

Writes from AGP/PCI (PCI semantics only) and

hub interface

ï£§ MSI direct to the System Bus

ï£§ Supports peer MSI between hub interface and AGP

ï£§ Provides redirection for IPI and upstream

interrupts to the System Bus

Accelerated Graphics Port (AGP) Interface

ï£§ Supports a single AGP device (either a connector

or on the motherboard)

ï£§ AGP Support

ï£§ Supports AGP 2.0 including 1x, 2x, and 4x AGP

data transfers and 2x/4x Fast Write protocol

ï£§ Supports only 1.5-V AGP electricals

ï£§ 32 deep AGP request queue

ï£§ PCI semantic (FRAME# initiated) accesses to

DRAM are snooped

ï£§ High priority access support

ï£§ Hierarchical PCI configuration mechanism

ï£§ Delayed transaction support for AGP-to-DRAM

FRAME# semantic reads that can not be serviced

immediately

ï£§ 32-bit upstream address support for inbound AGP

and PCI cycles

ï£§ 32-bit downstream address support for outbound

PCI and Fast Write cycles

ï£§ AGP Busy/Stop Protocol

ï£§ AGP Clamping and Sense Amp Control

Hub Interface to ICH3-M

ï£§ 266-MB/s, point-to-point hub interface to ICH3-M

ï£§ 66-MHz base clock

ï£§ Supports the following traffic types to the ICH3-M

ï£§ Hub interface-to-AGP memory writes

ï£§ Hub interface-to-DRAM

ï£§ CPU-to-hub interface

ï£§ Messaging

ï£§ MSI Interrupt messages

ï£§ Power Management state change

ï£§ SMI, SCI and SERR error indication

Power Management

ï£§ SMRAM space remapping to A0000h (128 KB)

ï£§ Supports extended SMRAM space above 256 MB,

additional 128K/256K/512K TSEG from Top of

Memory, cacheable (cacheability controlled by

CPU)

ï£§ APM Rev 1.2 compliant power management

ï£§ Suspend to System Memory

ï£§ ACPI 2.0 Support

ï£§ Intel SpeedStepï£ª technology support

ï£§ Cache coherency with CPU in sleep mode

ï£§ Dynamic Memory Power-down

Package

ï£§ Package options

ï£§ 593-pin FC-BGA (37.5 x 37.5 mm)

250687-002

Datasheet

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