82845MP Datasheet, PDF (94/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
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3.8.14.
IOBASE1 – I/O Base Address Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1Ch
F0h
Read/Write, Read Only
8 bits
This register controls the hosts to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit
Description
7:4
I/O Address Base. Corresponds to A[15:12] of the I/O address. Default=Fh
3:0
Reserved
3.8.15.
IOLIMIT1 – I/O Limit Address Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
Read/Write, Read Only
8 bits
This register controls the hosts to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.
Bit
Description
7:4
I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default=0h
3:0
Reserved (Only 16-bit addressing supported)
94
Datasheet
250687-002