82845MP Datasheet, PDF (64/157 Pages) Intel Corporation – Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)

Intel^®82845MP/82845MZ Chipset-Mobile (MCH-M)
R
3.7.21.
PAM[0:6] – Programmable Attribute Map Registers – Device #0
Address Offset:
Default Value:
Attribute:
Size:
90-96h
00h
Read/Write, Read Only
8 bits
The MCH-M allows programmable memory attributes on 13 Legacy memory segments of various sizes
in the 640 Kbytes to 1 Mbytes address range. Seven Programmable Attribute Map (PAM) Registers are
used to support these features. Cacheability of these areas is controlled via the MTRR registers in the
processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to
host initiator only access to the PAM areas. MCH-M will forward to main memory for any A.G.P., PCI,
or hub interface A initiated accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the host read accesses to the corresponding memory segment
are claimed by the MCH-M and directed to main memory. Conversely, when RE = 0, the host read
accesses are directed to PCI0.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory segment
are claimed by the MCH-M and directed to main memory. Conversely, when WE = 0, the host write
accesses are directed to PCI0.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 Kbytes in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and are defined in the following
table.
64
Datasheet
250687-002