HYB18T512400AF Datasheet, PDF (99/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 53 Timing Parameter by Speed Grade - DDR2-667
Parameter
Symbol
DDR2-667
Min.
Max.
Unit Note
1)2)3)4)5)6)
Data output hold time from DQS
t_QH
Data hold skew factor
t_QHS
Average periodic refresh Interval
t_REFI
Auto-Refresh to Active/Auto-Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B command period
t_RFC
t_RPRE
t_RPST
t_RRD
t_HP – t_QHS
340
—
—
105
0.9
0.40
7.5
10
—
—
7.8
3.9
—
1.1
0.60
—
—
ps
µs
13)14)
µs
13)15)
ns
1)
t_CK
12)
t_CK
12)
ns
16)17)
ns
17)18)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
t_RTP
t_WPRE
t_WPST
t_WR
WR
t_WTR
t_XARD
t_XARDS
7.5
0.35
0.40
15
t_WR/t_CK
7.5
2
7 – AL
—
—
0.60
—
—
—
—
ns
t_CK
t_CK
19)
ns
t_CK
ns
20)
t_CK
21)
t_CK
21)
Exit precharge power-down to any valid command (other t_XP
2
than NOP or Deselect)
—
t_CK
Exit Self-Refresh to non-Read command
t_XSNR
t_RFC +10
—
ns
Exit Self-Refresh to Read command
t_XSRD
200
—
t_CK
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V. See notes ^3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as low.
6) The output timing reference voltage level is V_TT. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
Data Sheet
99
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P