HYB18T512400AF Datasheet, PDF (97/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

7
Electrical Characteristics
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
7.1
Speed Grade Defenitions
Table 51 Speed Grade Definition Speed Bins for DDR667
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
IFX Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
t_CK
Parameter
Symbol Min. Max. Min. Max. —
Clock Frequency
@ CL = 3 t_CK
5
8
5
8
ns
1)2)3)4)
@ CL = 4 t_CK
3
8
3.75 8
ns
1)2)3)4)
@ CL = 5 t_CK
3
8
3
8
ns
1)2)3)4)
Row Active Time
t_RAS
45
70000 45
70000 ns
1)2)3)4)5)
Row Cycle Time
t_RC
57
—
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
12
—
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
12
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as low.
4) The output timing reference voltage level is V_TT. See section 8 for the reference load for timing measurements.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x t_REFI.
Table 52 Speed Grade Definition Speed Bins for DDR533 and DDR400
Speed Grade
DDR2–533C
DDR2–400B
Unit
IFX Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
–5
4–4–4
3–3–3
t_CK
Symbol Min. Max. Min. Max. —
Clock Frequency
@ CL = 3 t_CK
@ CL = 4 t_CK
@ CL = 5 t_CK
Row Active Time
t_RAS
Row Cycle Time
t_RC
RAS-CAS-Delay
t_RCD
Row Precharge Time
t_RP
5
8
5
3.75
8
5
3.75
8
5
45
70000 40
60
—
55
15
—
15
15
—
15
8
ns
8
ns
8
ns
70000 ns
—
ns
—
ns
—
ns
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Data Sheet
97
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P