HYB18T512400AF Datasheet, PDF (95/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6.1
I_DD Test Conditions
For testing the I_DD parameters, the following timing parameters are used:
Table 48 I_DD Measurement Test Conditions for DDR2–667C and DDR2–667D
Parameter
Symbol
–3
–3S
DDR2–667C 4–4–4 DDR2–667D 5–5–5
CAS Latency
CL_(IDD)
4
5
Clock Cycle Time
t_CK(IDD)
3
3
Active to Read or Write delay
t_RCD(IDD)
12
15
Active to Active / Auto-Refresh
t_RC(IDD)
57
60
command period
Active bank A to Active bank B
command delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
t_RRD(IDD)
t_RRD(IDD)
t_RAS.MIN(IDD)
t_RAS.MAX(IDD)
t_RP(IDD)
t_RFC(IDD)
7.5
10
45
70000
12
75
7.5
10
45
70000
15
75
Auto-Refresh to Active / Auto-Refresh t_RFC(IDD)
105
105
command period
Average periodic Refresh interval
t_REFI
7.8
7.8
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size); not on 256M component
Unit
t_CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Note
1)
2)
Table 49 I_DD Measurement Test Condition for DDR2–533C and DDR2–400B
Parameter
Symbol
–3.7
–5
Unit
DDR2–533C 4–4–4 DDR2–400B 3–3–3
CAS Latency
CL_(IDD)
4
3
t_CK
Clock Cycle Time
t_CK(IDD)
3.75
5
ns
Active to Read or Write delay
t_RCD(IDD)
15
15
ns
Active to Active / Auto-Refresh t_RC(IDD)
60
55
ns
command period
Active bank A to Active bank B t_RRD(IDD)
7.5
7.5
ns
command delay
10
10
ns
Active to Precharge Command t_RAS.MIN(IDD)
45
40
ns
t_RAS.MAX(IDD)
70000
70000
ns
Precharge Command Period
t_RP(IDD)
15
15
ns
Auto-Refresh to Active / Auto-
t_RFC(IDD)
105
105
ns
Refresh command period
Average periodic Refresh interval t_REFI
7.8
7.8
µs
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size); not on 256M component
Note
1)
2)
Data Sheet
95
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P