HYB18T512400AF Datasheet, PDF(21/117 Page) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512400AF Datasheet, PDF (21/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512[40/80/16]0AFâ[3/3S/3.7/5]

512-Mbit DDR2 SDRAM

Pin Configuration and Block Diagrams

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Figure 2

Note:

Pin Configuration for Ã8 components, P-TFBGA-60 (top view)

1. RDQS / RDQS are enabled by EMRS(1) command.

2. If RDQS / RDQS is enabled, the DM function is

disabled

3. When enabled, RDQS & RDQS are used as strobe

signals during reads.

4. VDDL and VSSDL are power and ground for the DLL.

They are isolated on the device from VDD, VDDQ, VSS

and VSSQ.

5. Ball position L8 is A13 for 512-Mbit and is Not

Connected on 256-Mbit.

Data Sheet

21

Rev. 1.3, 2005-01

09112003-SDM9-IQ3P

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