HYB18T512400AF Datasheet, PDF (68/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
CK, CK
CKE
"high"
> = t_RP
CMD P recharge
NOP
NOP
T3
> = t_RFC
AUTO
REFRESH
NOP
AUTO
REFRESH
> = t_RFC
NOP
NOP
Figure 53 Auto Refresh Timing
3.24.2 Self-Refresh Command
ANY
AR
The Self-Refresh command can be used to retain data,
even if the rest of the system is powered down. When
in the Self-Refresh mode, the DDR2 SDRAM retains
data without external clocking. The DDR2 SDRAM
device has a built-in timer to accommodate Self-
Refresh operation. The Self-Refresh Command is
defined by having CS, RAS, CAS and CKE held LOW
with WE HIGH at the rising edge of the clock. The
device must be in idle state and ODT must be turned off
before issuing Self Refresh command, by either driving
ODT pin LOW or using EMRS(1) command. Once the
command is registered, CKE must be held LOW to
keep the device in Self-Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and
is automatically enabled upon exiting Self Refresh.
When the DDR2 SDRAM has entered Self-Refresh
mode all of the external control signals, except CKE,
are “don’t care”. The DRAM initiates a minimum of one
Auto Refresh command internally within t_CKE period
once it enters Self Refresh mode. The clock is internally
disabled during Self-Refresh Operation to save power.
The minimum time that the DDR2 SDRAM must remain
in Self Refresh mode is t_CKE. The user may change the
external clock frequency or halt the external clock one
clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the
device can exit Self-Refresh operation.
The procedure for exiting Self Refresh requires a
sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self-Refresh Exit
command is registered, a delay of at least t_XSNR must
be satisfied before a valid command can be issued to
the device to allow for any internal refresh in progress.
CKE must remain HIGH for the entire Self-Refresh exit
period t_XSRD for proper operation. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self
Refresh mode after t_XSNR expires. NOP or deselect
commands must be registered on each positive clock
edge during the Self-Refresh exit interval t_XSNR. ODT
should be turned off during t_XSNR.
The use of Self Refresh mode introduces the possibility
that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh, the DDR2 SDRAM
requires a minimum of one extra auto refresh command
before it is put back into Self Refresh Mode.
Data Sheet
68
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P