HYB18T512400AF Datasheet, PDF (50/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.18
Read Command
The Read command is initiated by having CS and CAS
LOW while holding RAS and WE HIGH at the rising
edge of the clock. The address inputs determine the
starting column address for the burst. The delay from
the start of the command until the data from the first cell
appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven
LOW one clock cycle before valid data (DQ) is driven
onto the data bus. The first bit of the burst is
synchronized with the rising edge of the data strobe
(DQS). Each subsequent data-out appears on the DQ
pin in phase with the DQS signal in a source
synchronous manner. The RL is equal to an additive
latency (AL) plus CAS latency (CL). The CL is defined
by the Mode Register Set (MRS). The AL is defined by
the Extended Mode Register Set (EMRS(1)).
CLK
CLK, CLK
CLK
DQS,
DQS
DQ
t _CH t _CL
t _CK
t _DQSCK
DQS
DQS
t _RPRE
t _LZ
t DQSQmax
Dout
t QH
t _AC
t RPST
Dout
Dout
Dout
t _DQSQmax
t QH
Figure 24 Basic Read Timing Diagram
t _HZ
DO-Read
T0
T1
T2
T3
CK, CK
CMD
DQS,
DQS
DQ
Posted CAS
READ A
NOP
AL = 2
NOP
NOP
RL = 5
CL = 3
Figure 25 Read Operation Example 1
RL = 5 (AL = 2, CL = 3, BL = 4)
T4
NOP
T5
T6
T7
NOP
NOP
<= t DQSCK
NOP
Dout A0 Dout A1
Dout A2 Dout A3
T8
NOP
BRead523
Data Sheet
50
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P