HYB18T512400AF Datasheet, PDF (66/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.23.3 Read or Write to Precharge Command Spacing Summary
The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to
the Precharge commands to the same banks and Precharge-All commands.
Table 18 Minimum Command Delays
From Command To Command
Minimum Delay between “From Unit Note
Command” to “To Command”
READ
PRECHARGE (to same banks as
READ)
AL + BL/2 + max(t_RTP, 2) - 2×t_CK t_CK ¹⁾²⁾
READ w/AP
PRECHARGE-ALL
PRECHARGE (to same banks as
READ w/AP)
AL + BL/2 + max(t_RTP, 2) - 2×t_CK t_CK ¹⁾²⁾
AL + BL/2 + max(t_RTP, 2) - 2×t_CK t_CK ¹⁾²⁾
WRITE
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE)
AL + BL/2 + max(t_RTP, 2) - 2×t_CK t_CK ¹⁾²⁾
WL + BL/2 + t_WR
t_CK
2)
WRITE w/AP
PRECHARGE-ALL
PRECHARGE (to same banks as
WRITE w/AP)
WL + BL/2 + t_WR
WL + BL/2 + WR
t_CK
2)
t_CK
2)
PRECHARGE
PRECHARGE-ALL
PRECHARGE (to same banks as
PRECHARGE)
WL + BL/2 + WR
1
t_CK
2)
t_CK
2)
PRECHARGE-ALL
1
t_CK
2)
PRECHARGE-ALL PRECHARGE
1
t_CK
2)
PRECHARGE-ALL
1
t_CK
2)
1) RU{t_RTP(ns) / t_CK(ns)} must be used, where RU stands for “Round Up”
2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge
or precharge-all, issued to that bank. The precharge period is satisfied after t_RP,all depending on the latest precharge
command issued to that bank
Data Sheet
66
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P