HYB18T512400AF Datasheet, PDF (60/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clocks
NOP
AL = 2
RL = 6
>=tRAS
CL = 4
>=tRC
>=tRTP
Precharge
A
NOP
tRP
NOP
NOP
Bank A
Activate
CL = 4
Dout A0 Dout A1
Dout A2 Dout A3
BR-P624
Figure 43 Read Operation Followed by Precharge Example 4
RL = 6, (AL = 2, CL = 4), BL = 4, t_RTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD _{READ A}
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clks + 1
CL = 4
RL = 4
> = tR A S
NOP
NOP
P re ch a rg e
NOP
tR P
NOP
Bank A
A ctivate
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>=tR TP
first 4-bit prefetch
second 4-bit prefetch
Figure 44 Read Operation Followed by Precharge Example 5
RL = 4, (AL = 0, CL = 4), BL = 8, t_RTP > 2 CKs
BR-P404(8)
3.22.2 Write followed by Precharge
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 + t_WR. For write cycles, a delay
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(t_WR) referenced from the completion of the burst write
to the Precharge command. No Precharge command
should be issued prior to the t_WR delay, as DDR2
SDRAM does not support any burst interrupt by a
Precharge command. t_WR is an analog timing
parameter (see Chapter 7) and is not the programmed
value WR in the MR.
Data Sheet
60
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P