HYB18T512400AF Datasheet, PDF(56/117 Page) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512400AF Datasheet, PDF (56/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512[40/80/16]0AFâ[3/3S/3.7/5]

512-Mbit DDR2 SDRAM

Functional Description

3.20

Write Data Mask

One write data mask input (DM) for Ã4 and Ã8

components and two write data mask inputs (LDM,

UDM) for Ã16 components are supported on DDR2

SDRAMâs, consistent with the implementation on DDR

SDRAMâs. It has identical timings on write operations

as the data bits, and though used in a uni-directional

manner, is internally loaded identically to data bits to

insure matched system timing. Data mask is not used

during read cycles. If DM is HIGH during a write burst

coincident with the write data, the write data bit is not

written to the memory. For Ã8 components the DM

function is disabled, when RDQS / RDQS are enabled

by EMRS(1).

T$1 3 ( T$1 3 ,

$1 3$ 13

$1

$-

T70 2 %

T70 3 4

T

$3

$IN

$IN

$IN

T

$(

$IN

DONgTCARE

Figure 36 Write Data Mask Timing

-0 4 4

4

4

4

4

4

#,+

#,+

#-$

$13

$13

7RITE!

./0

T$13 3

7, 2,

./0

./0

./0

$1

$IN $IN $IN $IN

! ! ! !

$-

4

4

4

4

./0

./0

0REC H ARG E

./0

T72

T20

4

4

4

"ANK !

!CTIVA TE

./0

Figure 37 Write Operation with Data Mask Example

RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4

-0 44

Data Sheet

56

Rev. 1.3, 2005-01

09112003-SDM9-IQ3P

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