HYB18T512400AF Datasheet, PDF (64/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ w/AP
NOP
A10 ="high"
DQS,
DQS
DQ
AL = 1
NOP
NOP
AL + BL/2
NOP
NOP
NOP
tRP
Auto-Precharge Begins
NOP
Bank
A c tiv a te
CL = 3
RL = 4
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>= tRTP
Figure 49
first 4-bit prefetch
second 4-bit prefetch
BR-AP413(8)2
Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank
RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
DQS,
DQS
DQ
Posted CAS
READ w/AP
NOP
NOP
NOP
NOP
A10 ="high"
AL + tRTP + tRP
Auto-Precharge Begins
AL = 1
CL = 4
RL = 5
tRTP
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3
tRP
Bank
Activate
Figure 50
first 4-bit prefetch
BR-AP4133
Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank,
RL = 5 (AL = 1, CL = 4), BL = 4, t_RTP = 3 CKs
Data Sheet
64
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P