HYB18T512400AF Datasheet, PDF (34/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.10
Extended Mode Register EMR(2)
The Extended Mode Registers EMR(2) and EMR(3)
are reserved for future use and must be programmed
when setting the mode register during initialization.The
extended mode register EMR(2) is written by asserting
LOW on CS, RAS, CAS, WE, BA0 and HIGH on BA1,
while controlling the states of the address pins. The
DDR2 SDRAM should be in all bank precharge with
CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (t_MRD) must be satisfied to complete the write
operation to the EMR(2). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
"! "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! !
  

RE GA DD R
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Table 11 EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010_B)
Field Bits Type¹⁾ Description
BA2 16
reg.addr Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
BA1 15
BA0 14
A
[13:0] w
0_B BA2, Bank Address
Bank Adress[1]
1_B BA1, Bank Address
Bank Adress[0]
0_B BA0, Bank Address
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
1) w = write only
0_B A[13:0], Address bits
Data Sheet
34
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P