HYB18T512400AF Datasheet, PDF (53/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.19
Write Command
The Write command is initiated by having CS, CAS and
WE LOW while holding RAS HIGH at the rising edge of
the clock. The address inputs determine the starting
column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL –
1). A data strobe signal (DQS) has to be driven LOW
(preamble) a time t_WPRE prior to the WL. The first data
bit of the burst cycle must be applied to the DQ pins at
the first rising edge of the DQS following the preamble.
The t_DQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on
successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is
complete. The time from the completion of the burst
write to bank precharge is named “write recovery time”
(t_WR) and is the time needed to store the write data into
the memory array. t_WR is an analog timing parameter
(see Chapter 5) and is not the programmed value for
WR in the MRS.
DQS,
DQS
Figure 30 Basic Write Timing
t DQSH
DQS
DQS
t WPRE
t DQSL
Din
Din
Din
t _DS
t DH
t _WPST
Din
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
CMD
Posted CAS
WRITE A
DQS,
DQS
DQ
NOP
NOP
WL = RL-1 = 4
NOP
NOP
NOP
<= t DQSS
NOP
NOP
Completion of
the Burst Write
tWR
DIN A0 DIN A1 DIN A2 DIN A3
Figure 31 Write Operation Example 1
RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T9
Precharge
BW543
Data Sheet
53
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P