HYB18T512400AF Datasheet, PDF (19/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin Buffer
Type Type
Function
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
–
Not Connected
Other Pins ×4/×8 organizations
F9
ODT
I
SSTL On-Die Termination Control
Note: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is
applied to each DQ, DQS, DQS and DM signal for ×4 and
DQ, DQS, DQS, RDQS, RDQS and DM for ×8
configurations. For ×16 configuration ODT is applied to
each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM
signal. The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Other Pins ×16 organization
K9
ODT
I
SSTL On-Die Termination Control
Table 5 Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 6 Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Data Sheet
19
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P