HYB18T512400AF Datasheet, PDF (72/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
Tn
Tn+1
Tn+2
CMD
W RITE
w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid
C om m and
CKE
DQS,
DQS
WL = RL - 1 = 2
WL + BL/2 + WR
tIS
WR
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tIS
tXARD or
tXARDS *)
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 3
Figure 58 Active Power-Down Mode Entry and Exit Example after a Write Command with AP
WL = 2, WR = 3, BL = 4
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12. WR is the programmed value in the MRS mode register.
T0
T1
T2
CK, CK
CMD
CKE
Precharge
NOP
tIS
tRP
NOP
T3
NOP
Tn
Tn+1
Tn+2
NOP
NOP
NOP
tIS
tXP
Valid
Command
NOP
Precharge
Power-Down
Entry
Precharge
Power-Down
Exit
Figure 59 Precharge Power Down Mode Entry and Exit
Note: "Precharge" may be an external command or an internal precharge following Write with AP.
Data Sheet
72
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P