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HYB18T512400AF Datasheet, PDF (102/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d)
Parameter
Symbol DDR2–533C
DDR2–400B
Min.
Max.
Min.
Max.
Address and control input setup
time
tIS(base) 250
DQ low-impedance time from CK / tLZ(DQ)
CK
2 x tAC.MIN
DQS low-impedance from CK / CK tLZ(DQS)
Mode register set command cycle tMRD
time
tAC.MIN
2
OCD drive mode output delay
tOIT
Data output hold time from DQS tQH
Data hold skew factor
tQHS
Average periodic refresh Interval tREFI
0
tHP – tQHS
—
—
—
Auto-Refresh to Active/Auto-
tRFC
105
Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B
command period
tRPRE
tRPST
tRRD
0.9
0.40
7.5
10
Internal Read to Precharge
command delay
tRTP
7.5
Write preamble
Write postamble
Write recovery time for write
without Auto-Precharge
tWPRE
tWPST
tWR
0.35xtCK
0.40
15
Write recovery time for write with WR
Auto-Precharge
tWR/tCK
Internal Write to Read command tWTR
7.5
delay
Exit power down to any valid
command
tXARD
2
(other than NOP or Deselect)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
6 – AL
Exit precharge power-down to any tXP
2
valid command (other than NOP or
Deselect)
Exit Self-Refresh to non-Read
command
tXSNR
tRFC +10
Exit Self-Refresh to Read
command
tXSRD
200
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 3)4)5)6)
—
tAC.MAX
tAC.MAX
—
12
—
400
7.8
3.9
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
350
—
2 x tAC.MIN tAC.MAX
tAC.MIN
2
tAC.MAX
—
0
12
tHPQ – tQHS —
—
450
—
7.8
—
3.9
105
—
0.9
1.1
0.40
0.60
7.5
—
10
—
7.5
—
0.35xtCK
0.40
15
—
0.60
—
tWR/tCK
10
—
2
—
6 – AL
—
2
—
tRFC +10 —
200
—
Unit Note
1)2)3)4)5)
6)
ps 9)
ps 12)
ps 12)
tCK
ns
ps
µs 13)14)
µs 13)15)
ns 1)
tCK 12)
tCK 12)
ns 16)17)
ns 18)17)
ns
tCK
tCK 19)
ns
tCK
ns 20)
tCK 21)
tCK 21)
tCK
ns
tCK
Data Sheet
102
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
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