HYB18T512400AF Datasheet, PDF (71/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn+1
Tn+2
CK, CK
CMD
READ
NOP
READ w/AP
NOP
NOP
CKE
DQS,
DQS
DQ
AL = 1
CL = 3
RL = 4
RL + BL/2
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3
NOP
NOP
tIS
NOP
NOP
V a lid
Comm and
tIS
tXARD or
tXARDS *)
Figure 56
Active
Power-Down
Entry
Active
Power-Down
Exit
Active Power-Down Mode Entry and Exit Example after a Read Command
Act.PD 1
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
T0
T1
T2
CK, CK
CM D ^Precharge
*)
NOP
NOP
CKE
tRP
Precharge
Power-Down
Entry
T3
Tn
Tn+1
Tn+2
NOP
NOP
tIS
NOP
NOP
tIS
tXP
V alid
Com mand
NOP
Precharge
Power-Down
Exit
Figure 57 Active Power-Down Mode Entry and Exit Example after a Write Command
WL = 2, t_WTR = 2, BL = 4
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MR, address bit A12.
Data Sheet
71
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P