HYB18T512400AF Datasheet, PDF (54/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
CK, CK
CMD
Posted CAS
WRITE A
NOP
DQS,
DQS
DQ
WL = RL-1 = 2
T2
T3
T4
T5
T6
NOP
NOP
<= t DQSS
NOP
NOP
Completion of
the Burst Write
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Figure 32 Write Operation Example 2
RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
T7
T9
Precharge
Bank A
Activate
tRP
BW322
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
CMD
NOP
NOP
NOP
NOP
Posted CAS
READ A
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
tWTR
CL=3
RL=5
BWBR
Figure 33 Write followed by Read Example
RL = 5 (AL = 2, CL = 3), WL = 4, t_WTR = 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + t_WTR, where t_WTR
is the write-to-read turn-around time t_WTR expressed in clock cycles. The t_WTR is not a write recovery time (t_WR) but
the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
Data Sheet
54
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P