HYB18T512400AF Datasheet, PDF (63/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
DQS,
DQS
DQ
Posted CAS
READ w/AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 ="high"
AL + BL/2
Auto-Precharge Begins
AL = 2
CL = 3
RL = 5
tRAS
tRCmin.
tRP
Dout A0 Dout A1 Dout A2 Dout A3
Bank
A c tiv a te
BR-AP5231
Figure 47 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (t_RC Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ w/AP
NOP
NOP
NOP
NOP
NOP
NOP
Bank
A c tiv a te
NOP
DQS,
DQS
A10 ="high"
tRAS(min)
Auto-Precharge Begins
AL = 2
CL = 3
tRP
RL = 5
DQ
Dout A0 Dout A1 Dout A2 Dout A3
tRC
BR-AP5232
Figure 48 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (t_RAS Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP ≤ 2 CKs
Data Sheet
63
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P