HYB18T512400AF Datasheet, PDF (107/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3.3
Definition Data Setup (t_DS1) and Hold Time (t_DH1), Single-Ended Data Strobes
Data input setup time (t_DS1) with single-ended data
strobe enabled MR[bit10]=1, is referenced from the
input signal crossing at the V_IH(ac) level to the single-
ended data strobe crossing V_IH/L(dc) at the start of its
transition for a rising signal, and from the input signal
crossing at the V_IL(ac) level to the single-ended data
strobe crossing V_IH/L(dc) at the start of its transition for a
falling signal applied to the device under test.
Data input hold time (t_DH1) with single-ended data
strobe enabled MR[bit10]=1, is referenced from the
input signal crossing at the V_IH(dc) level to the single-
ended data strobe crossing V_IH/L(ac) at the end of its
transition for a rising signal and from the input signal
crossing at the V_IL(dc) level to the single-ended data
strobe crossing V_IH/L(ac) at the end of its transition for a
falling signal applied to the device under test.
The DQS signal must be monotonic between V_IL(dc.MAX
and V_IH(dc).MIN.
DQS
t _{DS t DH}
t _DS
t _DH
DQ
Figure 75 Data Setup and Hold Time (Single Ended Data Strobes)
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Data Sheet
107
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P