HYB18T512400AF Datasheet, PDF (98/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as low.
4) The output timing reference voltage level is V_TT. See section 8 for the reference load for timing measurements.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x t_REFI.
7.2
AC Timing Parameters
Table 53 Timing Parameter by Speed Grade - DDR2-667
Parameter
Symbol
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
t_AC
t_CCD
t_CH
t_CKE
t_CL
t_DAL
t_DELAY
t_DH(base)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
t_DQSS
t_DS(base)
t_DSH
t_DSS
t_HP
t_HZ
t_IH(base)
t_IPW
t_IS(base)
t_LZ(DQ)
t_LZ(DQS)
t_MRD
t_OIT
DDR2-667
Min.
–450
2
0.45
3
0.45
WR + t_RP
t_IS + t_CK + t_IH
Max.
+450
—
0.55
—
0.55
—
––
Unit Note
1)2)3)4)5)6)
ps
t_CK
t_CK
t_CK
t_CK
t_CK
7)
ns
8)
175
––
ps
9)
0.35
–400
—
t_CK
+400 ps
0.35
240
—
t_CK
—
ps
10)
– 0.25
100
+ 0.25 t_CK
—
ps
9)
0.2
—
t_CK
0.2
—
t_CK
MIN. (t_CL, t_CH)
11)
—
t_AC.MAX ps
12)
275
—
ps
9)
0.6
—
t_CK
200
—
ps
9)
2 x t_AC.MIN
t_AC.MAX ps
12)
t_AC.MIN
t_AC.MAX ps
12)
2
—
t_CK
0
12
ns
Data Sheet
98
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P