HYB18T512400AF Datasheet, PDF (106/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
8.3
Input and Data Setup and Hold Time
8.3.1
Definition for Input Setup (t_IS) and Hold Time (t_IH)
Address and control input setup time (t_IS) is referenced
from the input signal crossing at the V_IH(ac) level for a
rising signal and V_IL(ac) for a falling signal applied to the
device under test. Address and control input hold time
(t_IH) is referenced from the input signal crossing at the
V_IL(dc) level for a rising signal and V_IH(dc) for a falling
signal applied to the device under test.
CK
CK
t _IS t _IH
t _IS t _IH
Figure 73 Input Setup and Hold Time
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
8.3.2
Definition for Data Setup (t_DS) and Hold Time (t_DH), differential Data Strobes
Data input setup time (t_DS) with differential data strobe
enabled MR[bit10]=0, is referenced from the input
signal crossing at the V_IH(ac) level to the differential data
strobe crosspoint for a rising signal, and from the input
signal crossing at the V_IL(ac) level to the differential data
strobe crosspoint for a falling signal applied to the
differential data strobe enabled MR[bit10]=0, is
referenced from the input signal crossing at the V_IL(dc)
level to the differential data strobe crosspoint for a
rising signal and V_IH(dc) to the differential data strobe
crosspoint for a falling signal applied to the device
under test.
device under test.
DQS/DQS signals must be monotonic between
DQS/DQS signals must be monotonic between V_IL(dc).MAX and V_IH(dc).MIN.
V_IL(dc).MAX and V_IH(dc).MIN. Data input hold time (t_DH) with
DQS
DQS
t _DS t _DH
t _DS t _DH
Figure 74 Data Setup and Hold Time (Differential Data Strobes)
Data Sheet
106
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_{IL(ac) max}
V_SS
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P