HYB18T512400AF Datasheet, PDF (59/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
DQS,
DQS
DQ
Posted CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
NOP
Precharge
NOP
tRP
NOP
Bank A
Activate
AL = 1
CL = 3
RL = 4
>=tRAS
>=tRC
Dout A0 Dout A1
Dout A2 Dout A3 Dout A4 Dout A5
Dout A6 Dout A7
CL = 3
>=tRTP
first 4-bit prefetch
second 4-bit prefetch
BR-P413(8)
Figure 41 Read Operation Followed by Precharge Example 2
RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP ≤ 2 CKs
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
READ A
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clks
NOP
AL = 2
RL = 5
>=tRAS
CL = 3
>=tRC
>=tRTP
Precharge
NOP
tRP
NOP
Bank A
Activate
Dout A0 Dout A1
CL = 3
Dout A2 Dout A3
NOP
BR-P523
Figure 42 Read Operation Followed by Precharge Example 3
RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP ≤ 2 CKs
Data Sheet
59
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P