HYB18T512400AF Datasheet, PDF (39/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.13
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off termi-
nation resistance for each DQ, DQS, DQS, DM for ×4
and DQ, DQS, DQS, DM, RDQS (DM/RDQS share the
same pin) and RDQS for ×8 configuration via the ODT
control pin. DQS and RDQS are only terminated when
enabled by EMR(1).
For ×16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM
controller to independently turn on/off termination resis-
tance for any or all DRAM devices. The ODT function
can be used for all active and standby modes. ODT is
turned off and not supported in Self-Refresh mode.
VDDQ
VDDQ VDDQ
sw1
sw2
sw3
DRAM
Input
Buffer
Rval1
Rval2
Rval3
Rval1
Rval2
Rval3
Input
Pin
sw1
sw2
sw3
VSSQ
VSSQ
VSSQ
ODT_funct2
Figure 12 Functional Representation of ODT
Switch sw1, sw2 or sw3 are enabled by the ODT pin.
Selection between sw1, sw2 or sw3 is determined by
“Rtt (nominal)” in EMRS(1) address bits A6 & A2.
Target: Rval1 = Rval2 = Rval3 = 2 × Rtt
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Data Sheet
39
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P