HYB18T512400AF Datasheet, PDF (91/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6
Currents Measurement Specifications and Conditions
Table 44 I_DD Measurement Conditions
Parameter
Symbol Note
Operating Current -
One bank Active - Precharge
I_DD0
1)2)3)4)5)6)
t_CK = t_CK(IDD), t_RC = t_RC(IDD), t_RAS = t_RAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I_DD1
I_OUT = 0 mA, BL = 4, t_CK = t_CK(IDD), t_RC = t_RC(IDD), t_RAS = t_RAS.MIN(IDD), t_RCD = t_RCD(IDD), AL = 0,
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
1)2)3)4)5)6)
inputs are switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW; t_CK = t_CK(IDD);Other control and address inputs are stable; Data
bus inputs are floating_.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK(IDD); Other control and address inputs are
switching, Data bus inputs are switching_.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
I_DD2P
I_DD2N
I_DD2Q
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Active Power-Down Current
I_DD3P(0)
All banks open; t_CK = t_CK(IDD), CKE is LOW; Other control and address inputs are stable; Data
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
1)2)3)4)5)6)
Active Power-Down Current
I_DD3P(1)
All banks open; t_CK = t_CK(IDD), CKE is LOW; Other control and address inputs are stable, Data
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
1)2)3)4)5)6)
Active Standby Current
All banks open; t_CK = t_CK(IDD); t_RAS = t_RAS.MAX(IDD), t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH
between valid commands. Address inputs are switching; Data Bus inputs are switching;
I_DD3N
1)2)3)4)5)6)
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_(IDD);
t_CK = t_CK(IDD); t_RAS = t_{RAS.MAX.(IDD)}, t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching; I_OUT = 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_(IDD);
t_CK = t_CK(IDD); t_RAS = t_RAS.MAX(IDD), t_RP = t_RP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
I_DD4R
1)2)3)4)5)6)
I_DD4W
1)2)3)4)5)6)
Burst Refresh Current
I_DD5B
t_CK = t_CK(IDD), Refresh command every t_RFC = t_RFC(IDD) interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
1)2)3)4)5)6)
are switching.
Distributed Refresh Current
I_DD5D
t_CK = t_CK(IDD), Refresh command every t_REFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
1)2)3)4)5)6)
are switching.
Data Sheet
91
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P