HYB18T512400AF Datasheet, PDF (15/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Table 4 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin Buffer
Type Type
Function
Control Signals ×16 organization
K7
RAS
I
SSTL Row Address Strobe (RAS), Column Address Strobe (CAS),
L7
CAS
I
SSTL ^{Write Enable (WE)}
K3
WE
I
SSTL
L8
CS
I
SSTL Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL Bank Address Bus 1:0
G3
BA1
I
SSTL Note: BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also
determines if the mode register or extended mode register
is to be accessed during a MRS or EMRS(1) cycle
H8
A0
I
SSTL Address Signal 12:0, Address Signal 10/Autoprecharge
H3
A1
I
SSTL Note: Address Signal 10/Autoprecharge provides the row address
H7
A2
I
SSTL
for Activate commands and the column address and Auto-
J2
A3
I
SSTL
Precharge bit A10 (=AP) for Read/Write commands to
select one location out of the memory array in the respective
J8
A4
I
SSTL
bank. A10(=AP) is sampled during a Precharge command
J3
A5
I
SSTL
to determine whether the Precharge applies to one bank
J7
A6
I
SSTL
(A10=LOW) or all banks (A10=HIGH). If only one bank is to
K2
A7
I
SSTL
be precharged, the bank is selected by BA[1:0]. The
K8
A8
I
SSTL
address inputs also provide the op-code during Mode
K3
A9
I
SSTL
Register Set commands.
H2
A10
I
SSTL
AP
I
SSTL
K7
A11
I
SSTL
L2
A12
I
SSTL
L8
A13
I
SSTL Address Signal 13
Note: 512 Mbit components
NC
–
–
Note: 256 Mbit components
Address Signals ×16 organization
L2
BA0
I
SSTL Bank Address Bus 1:0
L3
BA1
I
SSTL
L1
NC
–
–
Data Sheet
15
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P