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HYB18T512400AF Datasheet, PDF (109/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
#+ # + FO RT)3A N DT)(
$1 3 $ 1 3 FO RT$ 3 AN D T$ (
62 % & TOAC
RE G IO N
DC TO6RE F
RE G IO N
DC TO6RE F
RE G IO N
62 % & TOAC
RE G IO N
TT$)33 TT$)((
TT$)33 TT$)((
6$$1
6)( ACMIN
6)( DCMIN
62% &
6), DCMAX
6), ACMAX
633
$E LTA4& 3
TA NG E NTLIN E
NOM IN ALLIN E
$E LTA42 ( $E LTA 42 3 $E LTA4 &(
3ETU P3LEW 2ATE
TA NG EN TLINE ;6 2%&DC 6), ACMA X=
$ELTA 4 &3
TA NG EN TLINE ;6 )(AC MIN 62%&DC =
3ETU P3LEW 2ATE
$ELTA 42 3
FALLIN G
SIGNA L
RISING
SIG NAL
TA NGE NTLIN E;62 %& DC 6),DCMA X=
(OLD3LEW 2ATE
$ELTA42(
TA N GEN TLINE ;6 )(DCMIN 6 2%&DC =
(OLD 3LEW2ATE
$ELTA 4& (
RISING
SIGNA L
FALLIN G
SIGNA L
Figure 77 Slew Rate Definition Tangent
Data Sheet
109
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P