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HYB18T512400AF Datasheet, PDF (31/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Table 8 Mode Register Definition (BA[2:0] = 000B)
Field
BT
Bits Type1)
3
w
BL
[2:0] w
Description
Burst Type
0B BT, Sequential
1B BT, Interleaved
Burst Length
Note: All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by
tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to
fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN.
3.6
DDR2 SDRAM Extended Mode Register Set (MRS)
The Extended Mode Register EMR(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
EMR(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
BA0, while controlling the state of the address pins
"! "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! !



 1OFF 2$ 1 3 $1 3 /#$ 0ROGRAM
2TT
!,
2TT $)# $, ,
REG A DDR
W W
W
W
W
W W W
-0"4  
Table 9 Extended Mode Register Definition (BA[2:0] = 001B)
Field
BA2
Bits Type1)
16 reg. addr.
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
BA1
15
BA0
14
0B BA2, Bank Address
Bank Address [1]
0B BA1, Bank Address
Bank Address [0]
0B BA0, Bank Address
Data Sheet
31
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
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