HYB18T512400AF Datasheet, PDF (74/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.27
Input Clock Frequency Change
During operation the DRAM input clock frequency can
be changed under the following conditions:
• During Self-Refresh operation
• DRAM is in Precharge Power-down mode and ODT
is completely turned off.
In the Precharge Power-down mode the DDR2-
SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
cycles after t_RP and t_AOFD have been satisfied the input
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After t_XP has been
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
re-lock period the DRAM is ready to operate with the
new clock frequency.
T0
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+1
Ty+2 Ty+3
Tz
CK, CK
CMD
CKE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DLL
RESET
NOP
V a lid
Command
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Frequency Change
occurs here
tXP
Stable new clock
before power-down exit
200 clocks
ODT is off during
DLL RESET
Frequ.Ch.
Figure 62 Input Frequency Change Example during Precharge Power-Down mode
3.28
Asynchronous CKE LOW Reset Event
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously LOW, immediately interrupting any
valid operation. DRAM requires CKE to be maintained
HIGH for all valid operations as defined in this data
sheet. If CKE asynchronously drops LOW during any
valid operation, the DRAM is not guaranteed to
preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay
(t_DELAY) before turning off the clocks. Stable clocks must
exist at the input of DRAM before CKE is raised HIGH
again. The DRAM must be fully re-initialized as
described the initialization sequence (Power On and
Initialization, step 4 through 13). DRAM is ready for
normal operation after the initialization sequence. See
Chapter 7 for t_DELAY specification.
stable clocks
CK, CK
tdelay
CKE
Figure 63
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
Asynchronous Low Reset Event
Data Sheet
74
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P