HYB18T512400AF Datasheet, PDF (35/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
3.11
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
initialization. The EMRS(3) is written by asserting low
on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
while controlling the state of the address pins.
"! "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! !
  

RE GA DD R
-0"4  
Table 12 EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010_B)
Field Bits Type¹⁾ Description
BA2 16 reg.addr Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
BA1 15
BA0 14
A
[13:0] w
0_B BA2, Bank Address
Bank Adress[1]
1_B BA1, Bank Address
Bank Adress[0]
1_B BA0, Bank Address
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
1) w = write only
0_B A[13:0], Address bits
Data Sheet
35
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P