HYB18T512400AF Datasheet, PDF (55/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
WRITE A
NOP
Posted CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3
SBR
Figure 34 Seamless Write Operation Example 1
RL = 5, WL = 4, BL = 4
The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
T0
T1
CK, CK
CM D _{W R ITE A}
NOP
T2
NOP
T3
T4
T5
NOP
W RITE B
NOP
T6
NOP
T7
NOP
T8
NOP
DQS,
DQS
DQ
WL = RL - 1 = 2
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 _{DIN A5 DIN A5 DIN A7} DIN B0 DIN B1 DIN B2 DIN B3 ^{DIN B4} DIN B5 DIN
SBW_BL8
Figure 35 Seamless Write Operation Example 2
RL = 3, WL = 2, BL = 8, non interrupting
The seamless non interrupting 8-bit write operation is supported by enabling a write command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
Data Sheet
55
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P