HYB18T512400AF Datasheet, PDF(22/117 Page) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512400AF Datasheet, PDF (22/117 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

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HYB18T512[40/80/16]0AFâ[3/3S/3.7/5]

512-Mbit DDR2 SDRAM

Pin Configuration and Block Diagrams

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Figure 3

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Pin Configuration for Ã16 components, P-TFBGA-84 (top view)

Note:

1. UDQS/UDQS is data strobe for DQ[15:8],

LDQS/LDQS is data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the

data mask signal for DQ[15:8]

3. VDDL and VDDSL are power and ground for the DLL.

They are isolated on the device from VDD, VDDQ, VSS

and VSSQ.

Data Sheet

22

Rev. 1.3, 2005-01

09112003-SDM9-IQ3P

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