MC68HC705JJ7 Datasheet, PDF (95/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9
Simple Synchronous Serial Interface
9.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications with peripheral devices or other MCUs. SIOP is implemented as a 3-wire master/slave
system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block diagram of
the SIOP is shown in Figure 9-1.
OSCILLATOR
CLOCK
$000A
÷2
SPR0
SPR1
CPHA
MSTR
SPE
LSBF
SPIR
SPIE
SIOP
INTERRUPT
SPIF
DCOL
CLOCK
DIVIDER
AND
SELECT
LATCH
QS
R
CLOCK
CONTROL
DIN
CLK
COMP
ERROR
DOUT
8-BIT SHIFT
REGISTER
PORTB LOGIC
PB7
SCK
PORTB LOGIC
PB6
SDI
PORTB LOGIC
PB5
SDO
FORMAT CONTROL
(LSB OR MSB FIRST)
$000B
$000C
SIOP
DATA REGISTER
(SDR)
INTERNAL M68HC05 BUS
Figure 9-1. SIOP Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
95