MC68HC705JJ7 Datasheet, PDF (65/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port B
7.3.9 PB7/SCK Logic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-12. The operations of the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK)
READ $0005
CLOCK SOURCE (MSTR)
SERIAL ENABLE (SPE)
WRITE $0005
DATA DIRECTION
REGISTER B
R
BIT DDRB7
WRITE $0001
READ $0001
WRITE $0011
RESET
PORT B DATA
REGISTER
BIT PB7
PULLDOWN
REGISTER B
R
BIT PDIB7
PB7
SCK
MASK OPTION REG. ($1FF1)
PULLDOWN
DEVICE
Figure 7-12. PB7/SCK Pin I/O Circuit
When using the PB7/SCK pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK
pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in
these cases.
a. If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial
data clock (SCK) from the SIOP.
b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK
pin to drive the serial data clock (SCK) into the SIOP.
2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of
the PB7/SCK pin.
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin.
4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB7 pulldown inhibit bit.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
65