MC68HC705JJ7 Datasheet, PDF (56/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
7.2.2 Data Direction Register A
The contents of the port A data direction register (DDRA) determine whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRA bit
disables the output buffer for the associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs and disabling the voltage
comparators from driving PA4 or PA5.
Address:
Read:
Write:
Reset:
$0004
Bit 7
0
6
5
4
3
2
1
0
DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA5–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears the DDRA5–DDRA0 bits.
1 = Corresponding port A pin configured as output and pulldown device disabled
0 = Corresponding port A pin configured as input
7.2.3 Pulldown Register A
All port A pins can have software programmable pulldown devices enabled or disabled globally by SWPDI
bit in the MOR. These pulldown devices are controlled by the write-only pulldown register A (PDRA)
shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns on the pulldown devices if the port
A pin is an input. Reading the PDRA returns undefined results since it is a write-only register; therefore,
do not change the value in PDRA with read/modify/write instructions. On the MC68HC705JP7 the PDRA
contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH,
and PDICL bits, which turns on all the port A and port C pulldown devices.
Address:
Read:
Write:
Reset:
$0010
Bit 7
PDICH
0
6
5
4
3
2
PDICL PDIA5 PDIA4 PDIA3 PDIA2
0
0
0
0
0
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
1
PDIA1
0
Bit 0
PDIA0
0
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4–PC7).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC
to be an input
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
56
Freescale Semiconductor