MC68HC705JJ7 Datasheet, PDF (38/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
With the edge-sensitive only trigger MOR option, a rising edge on a PA0:3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to a logic 0 and then rises again to a logic 1.
NOTE
If the port A pins are enabled as external interrupts, then a high level on any
PA0:3 pin will drive the state of the IRQ function such that the IRQ/V_PP pin
and other PA0:3 pins are to be ignored until ALL of the PA0:3 pins have
returned to a low level. Similarly, if the IRQ/V_PP pin is at a low level, the
PA0:3 pins will be ignored until the IRQ/V_PP pin returns to a high state.
4.5.3 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask
(IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s.
The ISCR also contains two control bits for the oscillators, external pin oscillator, and internal low-power
oscillator. Reset sets the IRQE and OM2 bits and clears all the other bits.
Address:
Read:
Write:
Reset:
$000D
Bit 7
IRQE
1
6
5
OM2
OM1
1
0
= Unimplemented
4
3
2
1
Bit 0
0
IRQF
0
0
0
R
IRQR
0
0
0
U
0
R
= Reserved
U = Unaffected
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Select Bits
These bits control the selection and enabling of the oscillator source for the MCU. One choice is the
internal low-power oscillator (LPO). The other choice is the external pin oscillator (EPO) which is
common to most M68HC05 MCU devices. The EPO uses external components like filter capacitors
and a crystal or ceramic resonator and consumes more power. The selection and enable conditions
for these two oscillators are shown in Table 4-2.
OM2 OM1
0
0
0
1
1
0
1
1
Table 4-2. Oscillator Selection
Oscillator
Selected
by CPU
Internal
External
Internal
Internal
Internal
Low-Power
Oscillator
(LPO)
Enabled
Disabled
Enabled
Enabled
External Pin
Oscillator
(EPO)
Disabled
Enabled
Disabled
Enabled
Power
Consumption
Lowest
Normal
Lowest
Normal
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
38
Freescale Semiconductor