MC68HC705JJ7 Datasheet, PDF (33/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4
Interrupts
4.1 Introduction
An interrupt temporarily stops normal program execution to process a particular event. An interrupt does
not stop the execution of the instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the central processor unit (CPU)
registers on the stack and loads the program counter with a user-defined vector address.
4.2 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of
the higher priority interrupt first. A higher priority interrupt does not actually
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
MOR
Control
Bit
Reset
Power-on logic
RESET pin
Low-voltage reset
—
Illegal address reset
COP watchdog
COPEN⁽¹⁾
Software
interrupt (SWI)
User code
—
IRQ/V_PP pin
—
External
interrupt (IRQ)
PA3 pin
PA2 pin
PA1 pin
PA0 pin
PIRQ⁽²⁾
Core timer
interrupts
TOF bit
RTIF bit
—
Programmable
timer interrupts
ICF bit
OCF bit
TOF bit
—
Serial interrupt
SPIF bit
—
Analog interrupt
CPF1 bit
CPF2 bit
—
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
Global
Hardware
Mask
—
—
I bit
I bit
I bit
I bit
I bit
Local
Software
Mask
—
—
IRQE bit
TOFE bit
RTIE bit
ICIE bit
OCIE bit
TOIE bit
SPIE bit
CPIE bit
Priority
(1 = Highest)
1
Same priority
as instruction
2
3
4
5
6
Vector
Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
$1FF2–$1FF3
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
33