MC68HC705JJ7 Datasheet, PDF (155/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

OSC11
tRL
RESET
INTERNAL
CLOCK⁽³⁾
4064 or 16 tcyc⁽²⁾
INTERNAL
ADDRESS
BUS⁽³⁾
INTERNAL
DATA
BUS⁽³⁾
1FFE
1FFF NEW PCH NEW PCL
NEW
NEW
Op
PCH
PCL
code
Notes:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064 t_cyc or short delay option of 16 t_cyc
3. Internal timing signal and data information not available externally
Figure 15-13. Stop Recovery Timing Diagram
Reset Characteristics
INTERNAL
RESET¹
RESET
PIN
INTERNAL
CLOCK⁽³⁾
tRPD
4064 or 16 tcyc⁽²⁾
INTERNAL
ADDRESS
BUS⁽³⁾
INTERNAL
DATA
BUS⁽³⁾
1FFE
1FFF NEW PCH NEW PCL
NEW
NEW
PCH
PCL
Notes:
1.Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout
2.Only if reset occurs during normal delay of 4064 t_CYC or short delay option of 16 t_CYC for initial power-up
or stop recovery.
3.Internal timing signal and data information not available externally
Figure 15-14. Internal Reset Timing Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
155