MC68HC705JJ7 Datasheet, PDF (109/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input Capture Registers
if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH, the LSB of the timer at ACRL must also be read to complete the read
sequence.
During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator
startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit
free-running counter or the TOF flag bit.
NOTE
To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
11.4 Input Capture Registers
The input capture function is a means to record the time at which an event occurs. The source of the event
can be the change on an external pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in
the analog subsystem. The ICEN bit in the analog subsystem control register (ACR) at $001D selects
which source is the input signal. When the input capture circuitry detects an active edge on the selected
source, it latches the contents of the free-running timer counter registers into the input capture registers
as shown in Figure 11-6.
NOTE
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set when
using voltage comparator 2 to trigger the input capture function.
PB3
AN3
TCAP
READ
ICRH
INPUT
SELECT
MUX
CPF2
FLAG
BIT
FROM
ANALOG
SUBSYSTEM
ICEN
CONTROL
BIT
RESET
EDGE
SELECT
& DETECT
LOGIC
LATCH
ICRH ($0014) ICRL ($0015)
16-BIT COUNTER
INPUT CAPTURE (ICF)
INTERNAL
DATA
BUS
READ
ICRL
÷4
INTERNAL
CLOCK
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-6. Timer Input Capture Block Diagram
Latching values into the input capture registers at successive edges of the same polarity measures the
period of the selected input signal. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
109