MC68HC705JJ7 Datasheet, PDF (23/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Registers
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
Register
Bit 7
Port A Data Register ^{Read: 0}
(PORTA) Write:
See page 55. _Reset:
Port B Data Register ^Read: _PB7
(PORTB) Write:
See page 58. _Reset:
Port C⁽¹⁾ Data Register ^Read: _PC7
(PORTC) Write:
See page 67. _Reset:
Analog Multiplex Register ^Read:
(AMUX) Write:
See page 73. _Reset:
HOLD
1
Data Direction Register A ^{Read: 0}
(DDRA) Write:
See page 56. _{Reset: 0}
Data Direction Register B ^Read:
(DDRB) Write:
See page 59. _Reset:
DDRB7
0
Data Direction Register C ^Read:
(DDRC) Write:
See page 67. _Reset:
DDRC7
0
Unimplemented
6
0
PB6
PC6
DHOLD
0
0
0
DDRB6
0
DDRC6
0
5
PA5
PB5
PC5
INV
0
DDRA5
0
DDRB5
0
DDRC5
0
4
3
PA4
PA3
Unaffected by reset
PB4
PB3
Unaffected by reset
PC4
PC3
Unaffected by reset
VREF MUX4
0
0
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
DDRC4 DDRC3
0
0
2
PA2
PB2
PC2
MUX3
0
DDRA2
0
DDRB2
0
DDRC2
0
1
PA1
PB1
PC1
MUX2
0
DDRA1
0
DDRB1
0
DDRC1
0
Bit 0
PA0
PB0
PC0
MUX1
0
DDRA0
0
DDRB0
0
DDRC0
0
$0008
Core Timer Status and Control Read:
Register (CTSCR) _Write:
See page 102.
Reset:
CTOF
0
RTIF
CTOFE
0
0
$0009
Core Timer Counter Register ^{Read: Bit 7}
6
5
(CTCR) Write:
See page 103. _{Reset: 0}
0
0
$000A
SIOP Control Register ^Read: _SPIE
SPE
LSBF
(SCR) Write:
See page 97. _{Reset: 0}
0
0
$000B
SIOP Status Register ^{Read: SPIF}
DCOL
0
(SSR) Write:
See page 99. _{Reset: 0}
0
0
= Unimplemented
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
0
0
RTIE
RT1
CTOFR RTIFR
0
0
0
1
4
3
2
1
0
0
0
0
0
MSTR
CPHA SPR1
SPIR
0
0
0
0
0
0
0
0
0
0
0
0
R = Reserved U = Unaffected
Figure 2-3. Register Summary (Sheet 1 of 3)
RT0
1
Bit 0
0
SPR0
0
0
0
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
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