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MC68HC705JJ7 Datasheet, PDF (154/164 Pages) Freescale Semiconductor, Inc – Microcontrollers
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Electrical Specifications
15.15 SIOP Timing (VDD = 3.0 Vdc)
Characteristic(1)
Symbol
Min
Frequency of operation
Master
Slave
fSIOP(M)
fSIOP(S)
0.25 x fOP
dc
Cycle time
Master
Slave
Clock (SCK) low time (fOP = 2.1 MHz)
SDO data valid time
SDO hold time
SDI setup time
SDI hold time
tSCK(M)
tSCK(M)
tSCKL
tV
tHO
tS
tH
4.0 x tcyc
—
1905
—
0
200
200
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
Typ
0.25 x fOP
—
4.0 x tcyc
—
—
—
—
—
—
Max
0.25 x fOP
525
4.0 x tcyc
1.9
—
400
—
—
—
15.16 Reset Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Low-voltage reset
Rising recovery voltage
Falling reset voltage
LVR hysteresis
VLVRR
2.4
VLVRF
2.3
VLVRH
30
POR recovery voltage(2)
VPOR
0
POR VDD slew rate(2)
Rising(2)
Falling(2)
SVDDR
—
SVDDF
—
RESET pulse width (when bus clock active)
tRL
1.5
RESET pulldown pulse width from internal reset
tRPD
3
3.4
4.4
3.3
4.3
70
—
—
100
—
0.1
—
0.05
—
—
—
4
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. By design, not tested
4.5
4
3.5
3
2.5
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95
TEMPERATURE IN °C
Figure 15-12. Typical Falling Low Voltage Reset
Unit
kHz
µs
ns
ns
ns
ns
ns
Unit
V
V
mV
mV
V/µs
tCYC
tCYC
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
154
Freescale Semiconductor
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