MC68HC705JJ7 Datasheet, PDF (101/164 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10
Core Timer
10.1 Introduction
This section describes the operation of the core timer and the computer operating properly (COP)
watchdog as shown by the block diagram in Figure 10-1.
$0009
OVERFLOW
CORE TIMER COUNTER REGISTER
÷4
BITS 0–7 OF 15-STAGE
RIPPLE COUNTER
INTERNAL
CLOCK
RESET
÷2
OSC1
INTERNAL CLOCK ÷ 1024
CORE TIMER
INTERRUPT
REQUEST
$0008
CORE TIMER STATUS/CONTROL REGISTER
RESET
$1FF0
COPR REGISTER
RESET
RTI RATE SELECT
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
POWER-ON
RESET
COP
WATCHDOG
RESET
Figure 10-1. Core Timer Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
101